What we do...

The Nanoelectronic Devices Computational Group is lead jointly by Karol Kalna and Antonio Martinez. It conducts research within the area of Simulation and Modelling of Semiconductor Devices.

Our main objectives are to:

  • Carry out advanced simulations and modelling of semiconductor devices
  • Employ 2D real space semiclassical and quantum transport simulation techniques for microelectronics and nanoelectronics planar devices
  • Employ and develop 3D real space classical, semiclassical and quantum transport simulation techniques for nanoelectronics planar and non-planar devices
  • Offer prestigious postgraduate research opportunities through research at the cutting edge development of nanoelectronics

Our research interests include:

  • Si and III-V FinFETs
  • Si Nanowires
  • Si and III-V MOSFETs including thin-body architectures
  • GaN HEMTs
  • Scanning probe microscopy modelling

Find out more about...

visualisation of electron density in multi-gate non-planar transistor
visualisation of electron density in multi-gate non-planar transistor
Research Tools
  • 3D quantum transport device simulations using Non-Equilibrium Green's Function (NEGF) technique including non-dissipative processes (eletron-phonon scattering)
  • Parallel 3D finite element ensemble Monte Carlo (MC) device simulations including 2D Schrödinger equation quantum corrections
  • 2D finite element ensemble Monte Carlo (MC) device simulations including quantum corrections
  • Parallel 3D finite element drift-diffusion (DD) device simulations including quantum corrections (density gradient)
Funding Awards
  • EPSRC Multiscale Modelling of Metal-Semiconductor Contacts for the Next Generation of Nanoscale Transistors (PI: K. Kalna, ended 2015)
  • EPSRC Career Acceleration Fellowship Quantum Simulations of Future Solid State Transistors (Fellow: A. Martinez, ended 2016)
  • FP7 Marie-Curie Fellowship 3D modelling of the performance and variability of high electron mobility transistors for future digital applications (PERSEUS) (Fellow: Natalia Seoane)
  • EPSRC Advanced Research Fellowship Modelling of Carrier Transport in Ultra Thin Body Transistors (Fellow: K. Kalna, ended August 2012)
  • Royal Society International Joint Project Finite Element 3D Monte Carlo Device Simulator for Multigate Transistors (PI: K. Kalna, ended February 2012)
Selected Publications
  • B. Ubochi, K. Ahmeda, S. Faramehr, P. Igić, A. Al-Khalidi, E. Wasige, and K. KalnaOperational Frequency Degradation Induced Trapping in Scaled GaN HEMTsaccepted to Microelectron. Reliab.(2017).
  • G. Indalecio, N. Seoane, K. Kalna and A. J. García-Loureiro, Fluctuation Sensitivity Map: A Novel Technique to Characterise and Predict Device Behaviour Under Metal Grain Work-Function Variability Effects, accepted to IEEE Trans. Electron Devices (2017).
  • M. A. Elmessary, D. Nagy, M. Aldegunde, Natalia Seoane, G. Indalecio, J. Lindberg, W. Dettmer, D. Perić, A. J. García-Loureiro, K. KalnaScaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulationsSolid-State Electron. 128 (2017) 17-24.
  • Olga Kryvchenkova, I. Abdullah, J. Macdonald, M. Elliott, T. Anthopoulos, Y.-H. Lin, P. Igić, K. Kalna, and R. J. Cobley, A non-destructive method for mapping metal contact diffusion in In2O3 thin-film transistorsACS Appl. Mater. & Interfaces 8, No. 38, (2016) 25631-25636.
  • B. Benbakhti, K. H. Chan, A. Soltani and K. KalnaDevice and Circuit Performance of the Future Hybrid III-V and Ge based CMOS TechnologyIEEE Trans. Electron Devices 63, No. 10, Oct. (2016) 3893 - 3899.
  • Natalia Seoane, M. Aldegunde, D. Nagy, M. A. Elmessary, G. Indalecio, A. J. García-Loureiro and K. KalnaSimulation Study of Scaled In0.53Ga0.47As and Si FinFETs for Sub-16 nm Technology NodesSemicond. Sci. Technol. 31, No. 7, (2016) 075005 (6pp).
  • G. Indalecio, A. J. García-Loureiro, N. Seoane and K. Kalna, Study of Metal-Gate Work-Function Variation using Voronoi cells: Comparison of Rayleigh and Gamma distributions, IEEE Trans. Electron Devices 63, No. 6, June (2016) 2625-2628.
  • M. A. Elmessary, D. Nagy, M. Aldegunde, J. Lindberg, W. G. Dettmer, D. Periç, A. J. García-Loureiro, and K. KalnaAnisotropic Quantum Corrections for 3D Finite Element Monte Carlo Simulations of Nanoscale Multigate Transistors, IEEE Trans. Electron Devices 63, No. 3, March (2016) 933-939.
  • N. Seoane, G. Indalecio, M. Aldegunde, D. Nagy, M. A. Elmessary, A. J. García-Loureiro and K. KalnaComparison of Fin Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs, IEEE Trans. Electron Devices 63, No. 3, March (2016) 1209-1216.
  • A. M. Lord, T. G. Maffeis, O. Kryvchenkova, R. J. Cobley, K. Kalna., D. M. Kepaptsoglou, Q. M. Ramasse, A. S. Walton, M. B. Ward, J. Köble and S. P. Wilks, Controlling the Electrical Transport Properties of Nanocontacts to Nanowires, Nano Lett. 15, 4248-4254 (2015).
  • C. J. Barnett, O. Kryvchenkova, L. S. J. Wilson, T. G. G. Maffeis, K. Kalna, and R. J. Cobley, The role of probe oxide in local surface conductivity measurements, J. Appl. Phys. 117, No. 17, May (2015) 174306 (7pp).
  • G. Indalecio, N. Seoane, M. Aldegunde, K. Kalna, and A. J. García-Loureiro, Variability Characterisation of Nanoscale Si and InGaAs Fin Field-Effect-Transistors at Subthreshold, J. Low Power Electron. 11, No. 2, 1-7 (2015).
  • M. Aldegunde and K. KalnaEnergy conserving, self-force free Monte Carlo simulations of semiconductor devices on unstructured meshes, Comput. Phys. Commun. 189, Apr. (2015) 31-36.
  • D. Nagy, M. A. Elmessary, M. Aldegunde, R. Valin, A. Martinez, J. Lindberg, W. G. Dettmer, D. Periç A. J. García-Loureiro, and K. Kalna, 3D Finite Element Monte Carlo Simulations of Scaled Si SOI FinFET with Different Cross-Sections, IEEE Trans. Nanotechnol. 14, No. 1, Jan. (2015) 93-100.
  • M. Aldegunde and K. KalnaEnergy conserving, self-force free Monte Carlo simulations of semiconductor devices on unstructured meshesaccepted to Comput. Phys. Commun. (2015).
  • S. Faramehr, K. Kalna and P. Igiç, Design and simulation of a novel 1400V–4000V enhancement mode buried gate GaN HEMT for power applicationsSemicond. Sci. Technol. 29, No. 11, Nov. (2014) 115020 (7pp).
  • M. Aldegunde, S. Hepplestone, P. Sushko, and K. KalnaMulti-scale simulations of a Mo/n+-GaAs Schottky contact for nano-scale III-V MOSFETs, invited for Semicond. Sci. Technol. 29 (2014).
  • G. Indalecio, M. Aldegunde, N. Seoane, K. Kalna and A. J. García-Loureiro, Statistical study of the influence of LER and MGG in SOI MOSFET, Semicond. Sci. Technol. 29, No. 4, Apr. (2014) 045005 (7pp).
  • O. Kryvchenkova, R. J. Cobley, and K. KalnaSelf-consistent modelling of tunnelling spectroscopy on III-V semiconductors, accepted to Appl. Surf. Sci. 295, March (2014) 173–179.
  • S. Faramehr, K. Kalna and P. Igiç, Drift-diffusion and hydrodynamic modelling of current collapse in GaN HEMTs for RF power application, Semicond. Sci. Technol. 29, No. 2, Feb. (2014) 025007 (11pp).
  • N. Seoane, G. Indalecio, E. Comesaña, M. Aldegunde, A. J. García-Loureiro and K. Kalna, Random dopant, line-edge roughness and gate workfunction variability in a Nano InGaAs FinFETIEEE Trans. Electron Devices 61, No. 2, Feb. (2014) 466-472.
  • J. Lindberg, M. Aldegunde, D. Nagy, W. G. Dettmer, K. Kalna, A. J. García-Loureiro, and D. Periç, Quantum corrections based on the 2-D Schrödinger equation for 3-D Finite Element Monte Carlo simulations of nanoscaled FinFETsIEEE Trans. Electron Devices 61, No. 2, Feb. (2014) 423-429.
  • M. Aldegunde, J. García-Loureiro, and K. Kalna3D Finite Element Monte Carlo Simulations of Multi-Gate Nanoscale Transistors, IEEE Trans. Electron Devices 60, No. 5, May (2013) 1561-1567.
  • N. Seoane, G. Indalecio, E. Comesaña, A. J. García-Loureiro, M. Aldegunde and K. Kalna3D Simulations of random dopant and metal gate workfunction variability in an In0.53Ga0.47As GAA MOSFET, IEEE Electron Device Lett. 34, No. 2, Feb. (2013) 205-207.
  • B. Benbakhti, A. Martinez, K. Kalna, G. Hellings, G. Eneman, K. De Meyer and M. Meuris, Simulation study of performance for a 20 nm gate length In0.53Ga0.47As Implant Free Quantum Well MOSFET, IEEE Trans. Nanotechnol. 11, 808-817 (2012)
  • A. Islam, B. Benbakhti, and K. Kalna, Monte Carlo study of ultimate channel scaling in Si and In0.3Ga0.7As bulk MOSFETs , IEEE Trans. Nanotechnol. 10, 1424-1432 (2011)
  • K. Kalna, N. Seoane, A. J. García-Loureiro, I. G. Thayne, and A. Asenov, Benchmarking of scaled InGaAs implant-free nanoMOSFETs, IEEE Trans. Electron Devices 55, 2297-2306 (2008)
  • M. Aldegunde, N. Seoane, and A. J. García-Loureiro, P. V. Sushko, A. L. Shluger, J. L. Gavartin, K. Kalna and A. Asenov, Atomistic mesh generation for the simulation of nanoscale metal-oxide-semiconductor field-effect transistors, Phys. Rev. E 77, 056702, 9 pages (2008)
  • B. Benbakhti, A. Soltani, K. Kalna, M. Rousseau, and J.-C. De Jaeger, Effects of self-heating on performance degradation in AlGaN/GaN-based devices, IEEE Trans. Electron Devices 56, 2178-2185 (2009)
  • A. Martinez, K. Kalna, P. V. Sushko, A. L. Shluger, J. R. Barker, and A. Asenov, Impact of body-thickness-dependent bandstructure on scaling of Double Gate MOSFETs: a DFT/NEGF study, IEEE Trans. Nanotechnol. 8, 159-166 (2009)