Photo from 2019

Professor Karol Kalna

Professor, Engineering

Telephone number

+44 (0) 1792 606678

Email address

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Research Links

Academic Office - B202
Second Floor
Engineering East
Bay Campus
Available For Postgraduate Supervision

About

Faculty Personal Web-Page.

Pioneered introduction of III-V MOSFETs for digital applications.
Developed parallel 3D finite element Schrödinger Equation quantum corrected drift-diffusion and Monte Carlo simulation toolboxes.
Studying a performance of nanoscale multi-gate transistors for future technology nodes (sub-10 nm technology nodes).
Simulating nanoscale transistor variability induced by materials and fabrication process using the 3D Monte Carlo and drift-diffusion toolboxes.
I coordinated simulation activities in the project "III-V MOSFETs for Ultimate CMOS" and in EU FP7 No. 1 STREP grant DUALLOGIC investigating nanoscale III-V MOSFETs.
I have more than 250 publications including 103 papers in journals like Nano Letters, IEEE T-ED, IEEE TNano, IEEE EDL, IEEE Access, IEEE J-EDS, and IEEE Microwave Theory Tech.; J. Appl. Phys.; Appl. Phys. Lett.; Phys. Rev. B and E; ACS Appl. Mater. & Interfaces, and Semicond. Sci. Technol, 20 invited talks.
I served in the programme committee of IEEE Nano 2009, 2011 ULIS 2010, IWCE 2015 and EDISON 2015 conferences, Programme Chair of IWCN 2017.
Jointly leading Nanoelectronic Devices Computational Group (NanoDeCo).

Areas Of Expertise

  • Simulation and modelling of semiconductor devices.

Career Highlights

Teaching Interests

Semiconductor Devices, Semiconductor Technology, Mathematics

Research

My research activities include physical modelling of nanoscale semiconductor transistors for digital applications using on 3D finite element ensemble Monte Carlo device simulations with integrated 2D finite element 2D Schrödinger equation solver. This research originates from my EPSRC Advanced Research Fellowship "Modelling of Carrier Transport in Ultra Thin Body Transistors". The 3D code was used to simulate nanoscale metal contacts within the EPSRC project "Multiscale Modelling of Metal-Semiconductor Contacts for the Next Generation of Nanoscale Transistors" in collaboration with Dr. Peter Sushko, at that time at University College London (now at Pacific Northwest National Laboratory).
I am running, jointly with Dr Antonio Martinez, a Nanoelectronic Devices Computational (NanoDeCo) Group. Our research interests include the modelling of MOSFETs including non-planar, 3D architectures as FinFETs (see below), nanosheet and nanowire FETs based on Si and III-V channels; ultra-fast pseudomorphic and metamorphic high electron mobility transistors (PHEMTs and MHEMTs) based on III-V materials; and a modelling of GaN HEMTs for RF and power applications. I was also a co-investigator for an EPSRC project on III-V MOSFETs and leading device simulations in an EU FP7 DUALLOGIC grant. [Extract from the personal web-page]

Award Highlights

EPSRC Advanced Research Fellow 2007-2012