Power Integrated Circuit Technology

LDMOS design optimisation using RESURF and Super Junction techniques is well documented. These methods are highly utilised to improve the figure of merit (i.e. maximise specific R_{ds (ON)} for desired breakdown voltage) of LDMOS devices. Simulation is an essential tool in the optimisation of these devices, and two dimensional cross sectional analysis is a base requirement for effective design. However, termination and end effects are often lost in these two dimensional views. Racetrack type designs can be used to eliminate end effects, and are usually employed for high voltage devices, but this method can present new problems with high voltage cross over and radius of curvature effects which often result in having to increase device dimensions or develop more complex designs. High side devices add another design challenge due to the requirement to isolate the source and body regions from the substrate.

Figures show typical low side (top) and high side (middle) n-channel LDMOS devices, with the high side source and p-well isolated from the substrate by a deep n-well. The deep n-well doping has been optimised to achieve minimal R_{ds (ON)} for 120V breakdown, but the real device will not reach this breakdown voltage due to the end effects of the large deep n-well, i.e. the physical result will be different from the one predicted by 2D simulation. Top down simulations have been used to observe and clarify this end effects. Bottom figure shows that the drain potential wraps around to the source via the undepleted deep n-well at the ends of the device, pinning the actual breakdown voltage to less than 50V.

A Lateral Double-diffused Magnetic sensitive MOSFET with integrated plate.

A magnetic sensitive device, Lateral Double-diffused Magnetic sensitive metal-oxide-semiconductor Field-Effect Transistor (LD MagFET), combining the sensory operation of conventional MagFETs and Hall plates is proposed. The sensor device is fully compatible with a high-voltage CMOS technology. It is found that the LD MagFET with integrated Hall plate exhibits an order of magnitude higher relative magnetic sensitivity in comparison with the split-drain silicon MagFETs in standard CMOS.

Due to its full compatibility with high-voltage CMOS technology, the proposed LD MagFET can be a suitable integrated sensor device for some high voltage applications such as magnetic sensitive (MS) smart-power ICs. Namely, the MS smart-power ICs consists of one or more magnetic sensors, high voltage/power devices (the ‘brawn’ of the system) and CMOS logic circuits (the system’s ‘brain’) fabricated on a common semiconductor substrate to maximize the overall IC performance, reduce power consumption and cost. The MS smart-power ICs detect the magnetic field in environment, convert it into analogue or digital electrical signal and deliver the result to a microprocessor or logic field-programmable gate array (FPGA) by means of an on-chip serial interface, for example. The MS smart-power ICs could be used for detecting position or rotation of the magnetized objects, portable battery-operated magnetodosimeters intended for monitoring the humans’ exposure to magnetic fields in particular working environments (hospitals or physics laboratories),  and/or wheel speed detection in automotive applications, amongst other various applications.

3D FEM prediction of the SML5020BN MOSFET device temperature distribution after t=1000s and equivalent RC network.

Physical structure and equivalent circuit of PT IGBT: A sub-circuit electro-thermal model of Punch-Trough (PT) IGBT with small set of temperature related fitting parameters was developed and implemented in SPICE. The model was validated against steady-state and transient measurements done on a 200A 850V PT IGBT module at 25⁰C, 75⁰C and 125⁰C.