Journal Articles

  1. & Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications. Microelectronics Reliability 99, 213-221.
  2. & Adaptive virtual resistance load sharing for resistive microgrids. Electric Power Systems Research 160, 17-26.
  3. & Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications. Microelectronics Journal 81, 94-100.
  4. & Universal and Seamless Control of Distributed Resources-Energy Storage for all Operational Scenarios of Microgrids. IEEE Transactions on Energy Conversion, 1-1.
  5. & Implementation and Stability Study of Dynamic Droop in Islanded Microgrids. IEEE Transactions on Energy Conversion 31(3), 821-832.
  6. & MPPT algorithm test on a photovoltaic emulating system constructed by a DC power supply and an indoor solar panel. Energy Conversion and Management 85, 460-469.
  7. & Development of an Optically Transparent Silicon CMOS Technology Platform for Biological Analysis. IEEE Sensors Journal, 1-1.
  8. Exploiting PV Inverters to Support Local Voltage—A Small-Signal Model. IEEE Transactions on Energy Conversion 29(2), 453-462.
  9. & LDMOSFET with drain potential suppression for 100V Power IC technology. Microelectronics Reliability 51(3), 529-535.
  10. & The use and validation of a laser scanner for computer aided design and manufacturing of wheelchair seating. Journal of Medical Engineering & Technology 35(6-7), 377-385.
  11. Design and analysis of a feedforward control scheme for a three-phase voltage source pulse width modulation rectifier using sensorless load current signal. IET Power Electronics
  12. Compact thermal model of a three-phase IGBT inverter power module.

Conference Contributions

  1. (2016). Developing a blended learning approach for the effective teaching of electronic circuit analysis. Presented at 2016 International Conference on Systems, Signals and Image Processing (IWSSIP),, 1-4.IEEE. doi:10.1109/IWSSIP.2016.7502742
  2. & (2009). Optimisation of 100V high side LDMOS using multiple simulation techniques. Presented at Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on,, 104-107. doi:10.1109/ISPSD.2009.5158012
  3. & (2008). A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture. Presented at Microelectronics, 2008. MIEL 2008. 26th International Conference on,, 177-179. doi:10.1109/ICMEL.2008.4559252