Power IC Technology Development


  • Carry out work in the area of power IC technology development, especially advanced device concepts, isolation devices and techniques, integrated sensors, Power IC applications
  • Carry out work related to device and circuit testing and characterisation
  • Carry out work related to development of 1D and 2D electro - thermal compact models of various modern power devices and employ them for power loss estimation

Find out more about

Research tools

Power IC Technology Research Tools

  • SILVACO commercial semiconductor technology and device simulator
  • TCAD Studio 2D FE device and technology simulator 

Funding awards

  • Power System on Chip Technology Development - TONIC, Dr Petar Igic – Principal Investigator, sponsor: TSB
  • Inverter Loss Simulation, Dr Petar Igic – Principal Investigator, sponsor: TOYOTA Motor Corporation
  • EPSRC Advanced Research Fellowship – Power IC Technology Development, Dr Petar Igic – Principal Investigator, sponsor: EPSRC
  • CDMOS IC Process Development, Dr Petar Igic – Principal Investigator, sponsor: Welsh Government


Laboratories and facilities include a Design and Modelling Laboratory equipped with multi-licenses for the industrial standard SILVACO TCAD software, CADENCE design tool, PSPICE and MATLAB software; well-equipped Device Characterization Laboratory, general purpose Power Electronics Laboratory, and Advanced Device Characterization Laboratory.

Selected publications

Power IC Technology Research Tools Testing Output Characteristics

Selected Publications:

  • N. Jankovic, D. Pantic, S. Batcup and P. Igic: “A lateral double-diffused magnetic sensitive metal-oxide-semiconductor field-effect transistor with integrated n-type Hall plate”, Applied Physics Letters, Vol. 100, 2012, p. 263507
  • P. Holland, M. Elwin, I. Anteney , J. Ellis, L. Armstrong, G. Birchby and P. Igic, “LDMOSFET with Drain Potential Suppression for 100V Power IC Technology”, Microelectronics and Reliability, Vol. 51 (3), March 2011, pp. 529 – 535]
  • N. Jankovic, P. Igic and N. Sakurai: “Compact model of the IGBT with localized lifetime control dedicated to power circuit simulations”, Solid State Electronics, doi:10.1016/j.sse.2009.10.014, Vol. 54, 2010, pp. 268 – 274
  • P. Holland and P. Igic: ”A p+/p-buffer/n-epi CMOS compatible high-side RESURF LDMOS transistor for Power IC applications”, Microelectronics Journal, doi:10.1016/j.mejo.2007.04.017
  • Igic, P., Starke, T.K.H.: ”Operating frequency and grounding issues regarding active junction isolation in the power integrated circuits”, Circuits, Devices and Systems, IEE Proceedings-, Volume 153,  Issue 1,  Feb. 2006 Page(s):79 – 81
  • T Starke and P Igic: “Transient blocking characteristics of highly efficient junction isolation based on standard CMOS process”, Solid-State Electronics, 49, pp. 1217-1222, 2005
  • T.K.H. Starke, P, Holland, P. Igic et al.: ”Novel Multiple Junction Isolation Structures With High Carrier Blocking Efficiency Based on Standard CMOS Process”, Applied Physics Letters, 84, number 25 , 2004
  • T. Starke, P. Holland, S. Hussain, W. Jamal, P. Mawby and Petar Igic: “Highly Effective Junction Isolation Structure for PICs Based on Standard CMOS Process”, IEEE Transactions on Electron Devices, 2004, 51, pp. 1178-1184
  • P. Igic, P.A. Mawby, M.S. Towers, W. Jamal and S. Batcup: “Investigation of the Power Dissipation During IGBT Turn-Off Using a New Physics-Based IGBT Compact Model”, Microelectronics and Reliability, 2002, 42, pp. 1045-1052
  • P. Igic and P.A. Mawby: "Investigation of the Thermal Stress Field in a Multilevel Aluminium Metallization in VLSI Systems", Microelectronics and Reliability, 2000, 40, pp. 443-450
  • D. Manic, P. Igic, P.A. Mawby, Y. Haddab, R.S. Popovic: "Mechanical Stress Related Instabilities in Silicon under Metal Coverage", IEEE Transactions on Electron Devices,December 2000, 47, pp. 2429-2437
  • P. Igic and P.A. Mawby: “Numerical Modelling of Stress-Induced Failure in sub-Micron Aluminium Interconnects in VLSI systems”, Solid State Electronics, 1999, 43, pp. 255-261
  • P. Igic and P.A. Mawby: “Finite Element Modelling of the Thermal Stress Field During Processing of VLSI Multilevel Structures”, Electronic Letters, 1998, 34, pp. 471-472