Senior Lecturer       EPSRC Advanced Research Fellow

Research Grants

Modelling of Carrier Transport in Ultra Thin Body Transistors

Principal Investigator (EPSRC Advanced Research Fellowship )

Summary: Aggressive scaling of the conventional metal-oxide-semiconductor field effect transistors is required by the International Technology Roadmap for Semiconductors as conventional devices will hit a limit beyond the 22 nm technology node. Novel, ultra-thin body transistors must be introduced into production in order to sustain the expected increase in device performance. Moreover, both the Silicon device body and the SiO₂ dielectric have to be replaced with a higher mobility semiconductor and higher dielectric constant materials.
The proposed fellowship research aims to develop a 'state-of-art' Monte Carlo device simulator which is capable of accurately modelling the low-dimensional properties of ultra-thin body transistors. The simulator will be employed to optimise the ultra-thin body architecture, to benchmark the prospective high mobility materials, and to investigate the impact of high-K dielectrics on channel mobility. It will also focus on the exploitation of different material crystal orientations in the channel.

Multiscale Modelling of Metal-Semiconductor Contacts for the Next Generation of Nanoscale Transistors

Principal Investigator (EPSRC Standard Research)

Summary: Contacts, made up of metal-semiconductor interfaces, are integral parts any semiconductor device. Compatibility of the metal and semiconductor components, homogeneity of structural and electrical characteristics of their interfaces, and robustness and durability of the contacts are crucial for the device proper functionality. Optimal operation of the contacts is a key to realisation of novel devices and development of new device concepts, including high mobility semiconductors based CMOS, tunnelling and spin-based transistors, tunnelling diodes, gas and infrared carbon-nanotube detectors, etc. Two major current trends in the semiconductor industry - miniaturisation of the devices and shift to new materials - pose the challenges for the contact technology: (i) robustness and stability of operation in ever smaller devices and (ii) compatibility of metal and semiconductor components. For example, the resistance of present day contacts is strongly affected by fluctuations in the currently being developed sub-22 nm technology.
Primary aims of the proposed research are
i) enabling and carrying out multiscale modelling of the optimal chemical compositions and structures of metal-semiconductor interfaces such that the Schottky barrier is minimal;
ii) analysis of the role of interface defects, strain, and disorder on the carrier transport in CMOS devices.

Finite Element 3D Monte Carlo Device Simulator for Multigate Transistors

Principal Investigator (Royal Society International Joint Project)

Summary: - to implement a MOSFET geometry within the parallel 3D finite element Monte Carlo simulator,
- to incorporate a density gradient method within the developed 3D Monte Carlo simulator to introduce quantum-mechanical corrections due to carrier confinement in the channel,
- to employ the parallel 3D Monte Carlo simulator to study the performance of multigate transistors like nanowires and FinFETs with realistic geometries,
- to incorporate physical models to evaluate the impact of atomicity in the multigate transistors like  trapped and fixed charges in the high-K dielectric gate stacks, and interface roughness and interface phonons between the semiconductor and the high-K dielectric layers,
- to investigate impact of atomicity induced variations on the performance of multigate transistors.

Research Interests

Simulations and Modelling of Nanoscale MOSFETs with a Channel Based on III-V and Si Semiconductors for Digital Applications

A finite element 2D heterostructure Monte Carlo simulator has been developed for modelling of metal-oxide-semiconductor field-effect transistors (MOSFETs) which incorporates: (i) realistic doping profiles; (ii) Fermi-Dirac statistics using self-consistent calculations of the Fermi energy and electron temperature; (iii) interface roughness and interface optical phonons scatterings; and (iv) quantum confinement effect using the effective quantum potential approach. This simulator is used to: (i) forecast the performance of III-V and metal-oxide-semiconductor field effect transistors (MOSFETs) in comparison with equivalent Si based MOSFETs, and (ii) study the performance and optimise the design of thin-body MOSFETs.

In addition, a finite element parallel 3D Monte Carlo simulator has been developed in collaboration with University of Santiago de Compostela for modelling of multi-gate MOSFETs and nanowires which incorporates: (i) realistic doping profiles generated analytically; (ii) interface roughness scatterings; and (iii) quantum confinement effect using the density gradient approach.

Simulations and Modelling of HEMTs Scaled into Sub-100 nm Dimensions Performing DC and RF Analysis

A ensemble heterostructure Monte Carlo simulator using finite element mesh has developed for modelling of high electron mobility transistors (HEMTs). This simulator which includes impact ionization; Schottky gate tunnelling using a particle based  model and quantum corrections.

Modelling of the Impact of Strain/Stress in GaN HEMTs and Thermal Transport

The electric properties of GaN-based HEMTs like the wide bandgap, high electron mobility, and high output power density provide an excellent opportunity to employ these devices in many power applications and applications for harsh environments. However, the current collapse and degradation of the device pose a significant hindrance to wider commercial use of GaN-based HEMTs. The device degradation is linked with a lattice defect formation caused by excessive stress driven by the electric field via the inverse piezoelectric effect. Thus, the collapse and the degradation are associated with charge trapping in the device. Commercial drift-diffusion simulations are used to investigate these effect on I-V characteristics of GaN-based HEMTs and optimise their design to minimise the current collapse and the device degradation.

Transport in Cascade Intersubband Semiconductor Lasers and in Separate Confinement Heterostructure Quantum Well Lasers

A self-consistent calculation approach has been developed to obtain electron intersubband relaxation and capture times, electron densities and temperatures as a function of applied electric field in cascade intersubband semiconductor lasers. Moreover, the electron capture time via electron-polar optical phonon and electron-electron interactions have been calculated and compared with measurements from pump-probe experiments in order to get insight into physical processes in separate confinement heterostructure quantum well lasers.

Open PhD Positions

1. Parallel 3D Finite Element Monte Carlo Device Simulations Of Multigate Transistors

You will continue in the development of a 3D finite element Monte Carlo device simulator in order to investigate and optimise future multigate semiconductor transistors with the complex 3D geometries for the sub-22 nm technology. This 3D simulator can run in parallel utilising the message passing interface (MPI) standard library. You will continue in the incorporating quantum-mechanical corrections to account for a carrier confinement in the channel using a density gradient method. Then, you will create unstructured meshes that will have mesh points at real atom positions in the crystal lattice of Si body and at the semiconductor-dielectric interface. Later, you extend the simulator by adapting high mobility materials like GaAs and InGaAs which are currently intensively researched for these novel device architectures.

This project will be supervised jointly by Dr Karol Kalna (EPSRC Advanced Research Fellow) and by Professor Oubay Hassan in Civil and Computational Engineering Centre, School of Engineering, Swansea University. In the last Research Assessment Exercise, the Times Higher rated Civil Engineering second in the UK.

Informal enquires can be addressed to k.kalna(at)swansea.ac.uk

Contacts, made up of metal-semiconductor interfaces, are integral part any semiconductor device and their quality is crucial for the device proper functionality. Two major current trends in the semiconductor industry - miniaturisation of the devices and shift to new materials - pose the challenges for the contact technology: (i) robustness and stability of operation in ever smaller devices and (ii) compatibility of the metal and semiconductor components. The introduction of new, high-mobility channel materials, like Ge and III-Vs, requires the search for compatible metals and brings new challenges to the contact fabrication.

The aims of this PhD research will be i) to enable and to carry out multiscale modelling of the optimal metal-semiconductor interfaces, such that the Schottky barrier is minimal and ii) to analyse the role of interface defects, strain, and disorder on the carrier transport in nanoscale multi-gate transistors. The research will be closely coordinated within the EPSRC grant "Multiscale Modelling of Metal-Semiconductor Contacts for the Next Generation of Nanoscale Transistors" in collaboration with Dr. Peter Sushko, University College London (UCL) and supported by IBM, TSMC, IMEC, and University of Glasgow. The PhD candidate will closely work with one post-doctoral researcher at Swansea and one post-doctoral researcher at UCL. He will help to bridge ab-initio modelling (DFT) across the metal-semiconductor interfaces using 3D transport Monte Carlo and Non-Equilibrium Green's Functions device simulations based on finite element mesh with atomistic resolution. The research in at forefront of the advanced modelling of access regions for a future 3D FinFET 22nm CMOS technology.

This PhD project will be supervised jointly by Dr Karol Kalna (Senior Lecturer and EPSRC Advanced Research Fellow) and by Dr Antonio Martinez (Senior Lecturer and EPSRC Acceleration Carrier Fellow), at School of Engineering, Swansea University. Ideally, you should have a background in physics, engineering, or computer science, with an interest in either atomistic scale semiconductor devices, or atomic scale material modelling, or high-performance computing, or computational modelling.

Informal enquires can be addressed to k.kalna(at)swansea.ac.uk.

Selected Publications

2011

1. A. Islam and K. Kalna, "Monte Carlo Study Of Ultimate Channel Scaling In Si and In_0.3Ga_0.7As Bulk MOSFETs", IEEE Trans. Nanotechnol. 10, No.6 (2011) 1424-1432.
2. B. Benbakhti, KH. Chan, E. Towie, K. Kalna, C. Riddet, X. Wang, G. Eneman, G. Hellings, K. De Meyer, M. Meuris, and A. Asenov, "Numerical analysis of the new implant-free quantum-well CMOS: DualLogic approach", Solid-State Electron. 63, No. 1 (2011) 14-18.
3. A. J. García-Loureiro, N. Seoane, M. Aldegunde, R. Valin, A. Asenov, A. Martinez and K. Kalna, "Implementation of the Density Gradient Quantum Corrections for 3D Simulations of Multigate Nanoscaled Transistors", IEEE Trans. Comput-Aided Des. Integr. Circuits Syst. 30, No. 6, June (2011) 841-851.
4. I. Aynul and K. Kalna, "Monte Carlo simulations of mobility in doped GaAs using self-consistent Fermi-Dirac statistics", Semicond. Sci. Technol. 26, No. 5, (2011) 055007 (9pp).
5. B. Benbakhti, K. Kalna, K. Chan, E. Towie, G. Hellings, G. Eneman, K. De Meyer, M. Meuris, and A. Asenov, "Design and analysis of a new In0.53Ga0.47As implant-free quantum-well device structure", Microelectron. Eng. 88, No. 4, (2011) 358-361.

   2010

6. A. Islam, B. Benbakhti and K. Kalna, "Electron velocity decline in Si nanoscales MOSFETs with the shortening of gate length",  J Phys.: Conf. Ser. 242, No. 1 (2010) 012011 (4 pages).
7. B. Benbakhti, J. S. Ayubi-Moak, K. Kalna, D. Lin, G. Hellings, G. Brammertz, K. De Meyer, I. Thayne, and A. Asenov, "Impact of Interface State Trap Density on the Performance Characteristics of Different III-V MOSFET Architectures", Microelectron. Reliab. 50 (2010) 360-364.
8. M. Aldegunde, Natalia Seoane, A.J. García-Loureiro, and K. Kalna, "Reduction of the self-forces in Monte Carlo simulations of semiconductor devices on unstructured meshes", Comput. Phys. Commun. 181, Jan. (2010) 24-34.

2009

9. B. Benbakhti, A. Soltani, K. Kalna, M. Rousseau, and J.-C. De Jaeger, "Effects of Self-Heating on Performance Degradation in AlGaN/GaN-Based Devices", IEEE Trans. Electron Devices 56, No. 10, Oct. (2009) 2178-2185.
10. J. S. Ayubi-Moak, K. Kalna, and A. Asenov, "Monte Carlo Simulations of In_0.75Ga_0.25As MOSFETs at 0.5 V Supply Voltage for High-Performance CMOS", Int. J. High Speed Electron. Systems 19, No. 1, (2009).
11. N. Seoane, A. Garcia-Loureiro, M. Aldegunde, K. Kalna and A. Asenov, "Impact of intrinsic parameter fluctuations on the performance of In_0.75Ga_0.25As implant free MOSFETs", Semicond. Sci. Technol. 24, No. 5, 055011 (2009).
12. A. Martinez, K. Kalna, P. V. Sushko, A. L. Shluger, J. R. Barker, and A. Asenov, "Impact of body-thickness-dependent bandstructure on scaling of double gate MOSFETs: a DFT/NEGF study", IEEE Trans. Nanotechnol. 8, No. 2, 159-166 (2009).

    2008

13. I. G. Thayne, R. J. W. Hill, D. A. J. Moran, K. Kalna, A. Asenov, and M. Passlack, "Comments on 'High Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm'", IEEE Electron Device Lett. 29, No. 10, 1085-1086 (2008).
14. K. Kalna, Natalia Seoane, A. J. Garcia-Loureiro, I. G. Thayne, and A. Asenov, "Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs", IEEE Trans. Electron Devices 55, No. 9, 2297-2306 (2008).
15. M. Aldegunde, Natalia Seoane, A. J. Garcia Loureiro, P. V. Sushko, A. L. Shluger, J. L. Gavartin, K. Kalna, and A. Asenov, "Atomistic mesh generation for the simulation of nanoscale metal oxide-semiconductor field effect transistors", Phys. Rev. E 77, 056702 (2008) [selected for Virtual Journal of Nanoscale Science & Technology (19 May, 2008 issue)].

    2007

16. A. Martinez, K. Kalna, A. Svizhenko, M. P. Anantram, J. R. Barker, and A. Asenov, "Impact of strain on scaling of double gate nanoMOSFETs using NEGF approach", Physica Status Sol. (c) 5, 47-51 (2007).
17. K. Kalna, R. Droopad, M. Passlack, and A. Asenov, "Monte Carlo simulations of InGaAs nano-MOSFETs", Microelectron. Eng. 84, 2150-2153 (2007).
18. A. Asenov, K. Kalna, I. Thayne, and R. J. W. Hill, "Simulation of implant free III-V MOSFETs for high performance low power nano-CMOS applications", Microelectron. Eng. 84, 2398-2403 (2007).
19. K. Kalna, J. A. Wilson, D. A. J. Moran, R. J. W. Hill, A. R. Long, R. Droopad, M. Passlack, I. G. Thayne, and A. Asenov, "Monte Carlo simulations of high performance implant free In0.3Ga0.7As nano-MOSFETs for low-power CMOS applications", IEEE Trans. Nanotechnol. 6, 106-112 (2007).
20. N. Seoane, A. J. Garcia-Loureiro, K. Kalna, and A. Asenov, "Impact of intrinsic parameter fluctuations on the performance of HEMTs studied with a 3D parallel drift-diffusion simulator", Solid-State Electron. 51, 481-488 (2007).
21. A. Martinez, K. Kalna, J. R. Barker and A. Asenov, "A study of the interface roughness effect in Si nanowires using a full 3D NEGF approach", Physica E 37, 168-172 (2007).

    2006

22. N. Seoane, A. J. Garcia-Loureiro, K. Kalna, and A. Asenov, "Statistical study of the effect of interface charge fluctuations in HEMTs using a 3D simulator", J. Comput. Electron. 5, 385-388 (2006).
23. M. Aldegunde, A. J. Garcia-Loureiro, K. Kalna, and A. Asenov, "Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator", J. Comput. Electron. 5, 311-314 (2006).
24. K. Kalna, Q. Wang, M. Passlack, and A. Asenov, "MC simulations of d-doping placement in sub-100 nm implant free InGaAs MOSFETs", Mater. Sci. Eng. B 135, 285-288 (2006).
25. K. Kalna, L. Yang and A. Asenov, "Fermi-Dirac statistics in Monte Carlo simulations of InGaAs MOSFETs", in "Nonequilibrium Carrier Dynamics in Semiconductors", Springer Proc. Phys. Ser. 110 (Springer Verlag, 2006).

    2005

26. A. J. Garcia-Loureiro, K. Kalna and A. Asenov, "Efficient three-dimensional parallel simulations of PHEMTs", Int. J. Numer. Model.-Electron. Netw. Device Fields 18, 327-340 (2005).

    2004

27. K. Kalna and A. Asenov, "Role of multiple delta doping in PHEMTs scaled to sub-100 nm dimensions", Solid-St. Electron. 48, 1223-1232 (2004).
28. Kalna, M. Borici, L. Yang and A. Asenov, "Monte Carlo simulations of III-V MOSFETs", Semicond. Sci. Technol. 19, S202-S205 (2004).

    2003

29. K. Kalna and A. Asenov, "Gate tunnelling and impact ionisation in sub 100 nm PHEMTs", IEICE Trans. Electron. E86-C, 330-335 (2003).

    2002

30. K. Kalna and A. Asenov, "Nonequilibrium and ballistic transport, and backscattering in decanano HEMTs: A Monte Carlo simulation study", Math. Comp. Simul. 62, 357-366 (2002).
31. K. Kalna and A. Asenov, "Nonequilibrium transport in scaled high electron mobility transistors", Semicond. Sci. Technol. 17, 579-584 (2002).
32. K. Kalna, S. Roy, A. Asenov, K. Elgaid and I. Thayne, "Scaling of pseudomorphic high electron mobility transistors to decanano dimensions", Solid-St. Electron. 46, 631-638 (2002).

    2001

33. K. Kalna, C. Y. L. Cheung, and K. A. Shore, "Electron transport process in quantum cascade intersubband semiconductor lasers", J. Appl. Phys. 89, 2001-2005 (2001).

    2000

34. K. Kalna, C. Y. L. Cheung, I. Pierce, and K. A. Shore, "Self-consistent analysis of carrier transport and carrier capture dynamics in quantum cascade intersubband semiconductor lasers", IEEE Trans. Microwave Theory. Technol. 48, 639-644 (2000).